1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which is electrically erasable and programmable and, more particularly, to an EEPROM capable of erasing data in a small unit.
2. Description of the Related Art
A flash EEPROM, which is one type of EEPROM and capable of electrically erasing data at once, includes a stacked memory cell transistor. The write of data to the flash EEPROM is performed by injecting channel hot electrons, and the erase of data therefrom is done by causing a Fowler-Nordheim tunnel current to flow. In this memory device, it is clearly effective to apply a negative voltage to the gate of the memory cell transistor when data is erased; therefore, a row decoder circuit for applying a negative voltage to a word line when data is erased, is required.
In the conventional EEPROM, all bits are erased at once or data is erased for each block of a large unit, but data cannot be erased for each block of a small unit.
Recently, a memory device capable of erasing data in a small unit has been developed, as is proposed in H. Kume et al., xe2x80x9cA 3.42 xcexcm2 Flash Memory Cell Technology Conformable to a Sector Erase,xe2x80x9d Symposium on VLSI Technology, 1991, pp 77-78. In this memory device, an erase block is designated for every word line, a negative voltage is applied to only the word lines of a block to be erased, and a high voltage of, e.g., 5 V is applied to the sources of all memory cell transistors. The word lines of non-selective blocks are set in a semi-selective mode, and a positive voltage lower than the source potential is applied to the word lines in order to prevent data from being erased by mistake.
In other words, a low voltage is applied to the gate of a non-selective memory cell, and a difference in potential between the source and gate thereof is reduced, thereby preventing so-called soft erase from being caused in the non-selective memory cell.
According to the memory device described above, only the selected word line has to be set to a low level (negative voltage) and the non-selected word line has to be set to a high level (positive voltage) in the erase mode, contrary to the read and write modes, and a row decoder circuit having such a voltage setting function is therefore needed.
Conventionally, two types of row decoder circuits, that is, a read/write type positive-voltage decoder and an erase type negative-voltage decoder consisting of a P-channel MOS transistor are arranged for each word line. A negative voltage is supplied from a negative-voltage supply circuit to the respective negative-voltage decoders. The positive-voltage decoder and the negative-voltage decoder of each row are separated from each other by interposing a negative-voltage stopping P-channel MOS transistor between them.
Since the two decoders have to be arranged for each word line as described above, the number of transistors constituting the row decoder circuit is increased, with the result that the area of the row decoder circuit occupied in an integrated circuit is greatly increased and the size of a chip is also increased.
A great voltage stress is applied to the negative-voltage stopping P-channel MOS transistor. For this reason, a gate oxide film on the MOS transistor has to be made thicker than the other circuit elements, which complicates a manufacturing process.
It is an object of the present invention to provide a nonvolatile semiconductor memory device comprising a row decoder circuit which is simpler in constitution than that of a conventional device.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns and each having a transistor having a source, a drain and a gate and capable of electrically erasing and rewriting data;
a plurality of word lines to which gates of the plurality of memory cells arranged in the same row of the memory cell array are connected in common;
a plurality of bit lines to which drains of the plurality of memory cells arranged in the same column of the memory cell array are connected in common; and
word line selection means for selecting one of the plurality of word lines in accordance with address information, applying a first voltage having a negative value to the selected one of the plurality of word lines in a data erase mode, and applying a second voltage of a positive value to each of non-selected word lines.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.